In this project, an efficient all-digital demodulator in digital communication receivers is proposed and implemented on a reconfigurable hardware platform in order to compensate timing and carrier phase offset. In the proposed design, a feedforward architecture which has better stability and performance than traditional feedback architectures is used in the timing synchronization loop. To mitigate the problem of oversampling rate of feedforward synchronizer, an innovative parallel demodulator architecture is presented which is optimized for high speed transmissions. This proposed architecture results in asynchronous data sampling where there is no need to adjust sampling rate of the analog to digital converter with an external feedback. To achieve good stability conditions in the presence of loop delay in carrier recovery loop, an appropriate compensation method is utilized. Since the delay compensation technique is applied, the proposed architecture is well suited for VLSI implementations. In this project a numerically controlled oscillator with reduced lookup table is used to generate sine and cosine waves. The proposed architecture is used to implement QAM digital communication receiver on a Xilinx FPGA platform achieving higher clock rate. Implementation results show that our design has a good performance for different modulation orders as well as excellent robustness against loop delays and variations in the loop