The scaling down of CMOS circuits has resulted in increasing the sub-threshold leakage current with the decrease in the threshold voltage. LECTOR is a method to decrease the problem of leakage in CMOS circuits, it includes two extra leakage control transistors, which are self-controlled, in the pathway from supply to ground which offers the extra resistance which will reduce the problem of leakage current in the CMOS circuit. This paper concentrates on the analysis of leakage current in basic CMOS Inverter employing LECTOR technique using Cadence 45nm technology.