In modern trends, the demand for memory has been increases tremendously. Also it is well known that in low scale technology reliability and variations average power consumption are the main design challenges. As Static Random Access Memory (SRAM) is used in high speed applications such as cache memory and occupies about 90% of silicon area various research works have been done to trim down its power consumption. This paper represents the issues in nanoscale memory design, which will have a ubiquitous presence in commercial electronic market.