The shrinking of device size has led to use of lower supply voltage which in turn requires the lowering of threshold voltage. This has led to the increase in sub-threshold leakage current which results in increased power dissipation. In this paper we have utilized LECTOR technique to implement combinational circuits like NAND, NOR and EX-OR and then a comparative analysis of power and delay has been carried out. The simulation has been carried out on 180nm CMOS technology using Cadence Virtuoso tool.