This paper presents the design exploration and applications of combinational VLSI designs for multimedia/DSP purposes. This paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern. The objective of a good multiplier is to provide a physically compact, good speed and low power-consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. In this project we used Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification on targeted FPGA. Keywords-- Modified Booth encoder, low power multiplier, detection logic unit.