Designing multipliers that are of speedy, low power, and standard in layout are of generous research interest. Wallace tree multiplier is one of the multiplier, which is used to accomplish high speed and low power multiplier and to condense the number of partial products generated in multiplication process. To trim down the time Wallace Tree adder structures have been used to sum the partial products .In general Wallace tree multipliers are existing in 8*8 bit multipliers and 16 bit multipliers. In this paper we put forward a 32 bit high level Wallace tree multiplier structure is investigated and assessed. A 32 bit Wallace high-speed multiplier uses full adders and half adders, 4:2 compressor, 3:2 compressor in their declining phase. The Wallace tree multiplier is consisting of 64 registers, 64 flip flops and 3 half adders as well as 960 full adders with logic time delay is 53.198 ns and off set time delay is 7.6 ns, having total memory usage is 191.132MB. The design is efficiently mapped to Hardware Resources in SPARTAN-3 FPGA. The design is implemented, simulated and synthesized by using Verilog.