Parallel prefix adder is used for speeding up the logical operation of the system. Implementation of parallel prefix adder's structure in VLSI have effective performance. The different types of parallel prefix adder structures are Kogge-Stone , Brent-Kung, Sparse Kogge-Stone adder etc. have been proposed previously. Among them Kogge- Stone adder is the fastest adder structure. Sparse Kogge-Stone adder is the sub-type of Kogge-Stone adder in which it uses less black cells and grey cells as compared with the Kogge-Stone adder and final sum is calculated through ripple carry adder. In this paper, firstly Basic Sparse Kogge Stone adder is implemented and secondly, implementation of the Sparse Kogge-Stone adder using carry select logic is performed that result in reduction in critical path delay and increase in speed. On verifying its synthesis report it is observed that it requires 72 of its total numbers of slices with minimum path delay of 18.830 ns and a maximum frequency of 53.10 MHz of modified Sparse Kogge-Stone adder. On comparing with Basic Sparse Kogge-Stone adder and previous reference paper, it is observed that the modified design shows the improvement in speed with considerable reduction in delay.